In recent years, use of chip type electronic components has been rapidly increasing as electronic equipment requires reduction in size and weight and the surface mount technology progresses forward. This applies to capacitors, also, and a reduction in size and an increase in per unit capacity are required for chip type solid electrolytic capacitors.
A description of a conventional chip type solid electrolytic capacitor is made in the following:
FIG. 9 shows a prior art chip type solid electrolytic capacitor. Reference symbol 21 is a capacitor element in FIG. 9. The capacitor element 21 is prepared, according to a widely known method, by forming an oxide layer 23, an electrolyte layer 24 and a carbon layer 25 in succession on the surface of a porous anode body 22 formed by powder molding and sintering of a valve metal with an anode lead wire 27 buried inside thereof. And, one end of the anode lead wire 27 is exposed. Then a cathode layer 26 composed of a silver paint is formed over the carbon layer 25.
The anode lead wire 27 extending out of the capacitor element 21 is cut with the necessary portion thereof left and then the cathode layer 26 of the capacitor element 21 is connected with and fixed to a cathode lead frame 28a formed on a belt like metal frame 28 by means of a conductive adhesive 31.
By resistance welding, the anode lead wire 27 is joined with and fixed to an anode lead frame 28b formed on the same frame 28.
Next, the capacitor element 21 fixed to the foregoing frame 28 is encapsulated with an electrically insulating resin by a transfer molding method to form a resin package 32. The cathode lead frame 28a and anode lead frame 28b of the frame 28 are cut to a predetermined length to serve as a terminal. And, a capacitor element 21 is cut off from the frame 28.
Then, both lead frames 28a and 28b are bent along the periphery of the resin package 32 to make a cathode terminal 28d and an anode terminal 28e, respectively, thus completing a chip type solid electrolytic capacitor.
However, with the foregoing prior art chip type solid electrolytic capacitor, the cathode lead frame 28a of the frame 28 has a gutter-like guide 29 formed by bending both edges upward for aligning the position of the capacitor element 21 and is bent at a shoulder 30 downward by one step in a step-wise manner to provide a place for connection beneath the cathode layer 26 of the capacitor element 21. The connection is performed by means of the conductive adhesive 31. Furthermore, since the cathode lead frame 28a and anode lead frame 28b of the frame 28 are respectively bent to form the cathode terminal 28d and anode terminal 28e after the capacitor element 21 has been encapsulated with an electrically insulating resin, the volume of the capacitor element 21 cannot be increased if the capacitor element 21 is to be contained in the predetermined volume of the resin package 32, thus presenting a problem to be solved.
In other words, a section provided on the end part of the cathode lead frame 28a for the connection with the cathode layer 26 by the shoulder 30, where the cathode lead frame 28a is bent downward by one step in a step-wise manner, a part of the cathode terminal 28 bent along the periphery of the resin package 32 and a part of the anode terminal 28e together prevent the capacitor element 21 from being increased in volume.
Further, when the anode lead wire 27 is joined with the anode lead frame 28b by resistance welding, the junction between the anode lead frame 28b and the anode lead wire 27 tends to become long due to a flattening process applied to the place of the anode lead frame 28b where the anode lead wire 27 is joined, thereby causing a problem of hindering the volume of the capacitor element 21 from being increased.
The present invention deals with these problems involved with prior art chip type solid electrolytic capacitors and serves the purpose of providing a chip type solid electrolytic capacitor, whereby large capacity in the smallest possible size is realized, and disclosing its manufacturing method.